This invention relates to computer systems. More particularly, the present invention relates to a new and improved bus snooping device and technique for maintaining coherency between a main memory and one or more cache memories in a computer system having a bus, such as an Advanced High-Performance Bus (AHB), that does not have built-in bus snooping capabilities.
Computer systems typically incorporate information (e.g. data and/or command) xe2x80x9ccachingxe2x80x9d features into some components, such as central processing units (CPU""s). The components use a copy of the information maintained in a high-speed memory (cache memory) separate from a slower main memory of the computer system, in which the original, or xe2x80x9cprimary,xe2x80x9d copy of the information is kept. Some computer systems, particularly high-end computer systems, incorporate more than one CPU or other component that caches information, i.e. multiple xe2x80x9ccaching devices.xe2x80x9d In some of the computer systems that have multiple caching devices, it is sometimes possible for more than one of the caching devices to cache the same information. Therefore, it is important to ensure, after one caching device alters its copy of the information or the original copy in the main memory, that the other caching devices using the same information do not use the previous information, which has become old, or xe2x80x9cstale.xe2x80x9d In other words, the computer system must maintain xe2x80x9ccoherencyxe2x80x9d between information stored in the main memory and copies of the information stored in one or more cache memories.
In order to prevent caching devices from using stale information and in order to maintain cache coherency, xe2x80x9cbus snoopingxe2x80x9d features have been incorporated into bus systems through which the caching devices communicate. A protocol for the bus system includes signals which enable bus snooping. Bus snooping essentially monitors activity on the bus system that indicates a change to a copy of the information which has been cached, so that the other copies of the information can be updated or invalidated. The xe2x80x9cmonitoringxe2x80x9d is commonly referred to as xe2x80x9csnooping.xe2x80x9d
A typical prior art bus system 100, which incorporates bus snooping features, as shown in FIG. 1, generally includes command lines 102, address lines 104 and data, lines 106 to which bus devices 108, 110 and 112 (e.g. bus controllers, bus masters, CPU""s, etc.) are connected. Through the command lines 102, the bus system 100 transfers a xe2x80x9cwritexe2x80x9d signal (not shown) that is asserted by the bus device (e.g. 108) that is attempting to write information (a xe2x80x9cmasterxe2x80x9d device, e.g. a CPU, direct memory access xe2x80x9cDMAxe2x80x9d device, etc.) to indicate to the bus device (e.g. 110) that is to receive the information (a xe2x80x9cslavexe2x80x9d device, e.g. the main memory, etc.) that a write request is being issued. The master bus device 108 places the address to which the information is to be written in the slave bus device 110 onto the address lines 104.
The caching devices (e.g. bus device 112) that are not involved in the write request monitor the write signal (not shown) on the command lines 102. When the write signal is asserted, the caching bus device 112 reads the address lines 104 and compares the address to the addresses of the information that the caching bus device 112 has cached. Upon a match, the caching bus device 112 invalidates the cached information, so the caching bus device 112 will have to read the new information from the slave bus device 110 when the caching bus device 112 next accesses the information.
Through the command lines 102 the bus system 100 transfers a xe2x80x9choldxe2x80x9d signal (not shown) for preventing the master bus device 108 from performing the write command until after the other caching devices (caching bus device 112) have completed the write-signal-snooping and address-comparing functions. After the caching bus device 112 completes the snooping and comparing functions, the caching bus device 112 releases, or deasserts, the hold signal, so the master and slave bus devices 108 and 110 can continue with the write command.
Among bus systems that do not have bus snooping capabilities is the Advanced High-Performance Bus (AHB) (TM) from ARM Limited. The AHB is described in the AMBA (Advanced Microcontroller Bus Architecture) (TM) Specification (Rev 2.0) from ARM Limited. The disclosure of this specification is incorporated herein by this reference. Generally, the AHB is a high-performance xe2x80x9csystem bus,xe2x80x9d as distinguished from a xe2x80x9cperipheral busxe2x80x9d (e.g. Peripheral Component Interconnect xe2x80x9cPCI,xe2x80x9d Industry Standard Architecture xe2x80x9cISA,xe2x80x9d etc.), on which the CPU, a Direct Memory Access (DMA), a Digital Signal Processor (DSP), an external memory interface, a peripheral bus bridge and/or an internal memory, among other devices designed to the AMBA Specification (Rev. 2.0), are connected for fast access.
The AMBA Specification (Rev. 2.0) does not include bus snooping capabilities and the AHB protocol described therein does not include signals to maintain cache coherency between devices connected to the AHB. Information cannot be stored in cache memory and shared between caching devices in a computer system having the AHB because the computer system may not operate in a consistent or predictable manner since cache coherency cannot be maintained in the computer system. Therefore, since the AHB does not support bus snooping, only one caching device, such as a master device 118 as shown in FIG. 2 having a processor 120 and a cache memory 122, may be connected to the AHB 124. Otherwise, if there is more than one caching device, each caching device must not be allowed to cache the same information. With only one caching device (master device 118), however, it is not possible for two devices on the AHB 124 to have duplicate copies of information that both can use and/or alter, so there is no risk of a device using stale information. Likewise, there is no signal that is equivalent to the hold signal (not shown, but described above with reference to FIG. 1) transferred through the command lines 102 (FIG. 1) that can delay a write request issued by the master device 118 onto the AHB 124 for the purpose of enabling bus snooping.
Without the equivalent of a hold signal (not shown) transferred through the command lines 102 (FIG. 1) to enable snooping of write requests, the procedure for a master device 126,128 or 130, as shown in FIG. 3, to establish a connection with a slave device 132,134 or 136 through the AHB 124 is briefly described here. One of the master devices (e.g. 130) requests control of the AHB 124 in order to access one of the slave devices (e.g. 136). An arbiter 138 determines whether to grant the access. Upon grant, the requesting master device 130 and the slave devices 132-136 assert, or exchange, a series of signals according to the AMBA Specification (Rev. 2.0) to establish the connection between the requesting master device 130 and the requested slave device 136. The connection is generally established upon selection of an asserted xe2x80x9creadyxe2x80x9d signal 140 (among other command, address and data lines 142 of the AHB 124) from the requested slave device 136 by a decoder 144. The decoder 144 selects the asserted ready signal 140 of the requested slave device 136 by decoding an address of the requested slave device 136 (supplied by the requesting master device 130 on the other command/address/data lines 142) into a xe2x80x9cselectxe2x80x9d signal 148, which causes a multiplexor 146 to pass the asserted ready signal 140 of the requested slave device 136 as a selected ready signal 150 to the master devices 126-130 and the arbiter 138. Only the requesting master device 130 responds to the selected ready signal 150.
It is with respect to these and other background considerations that the present invention has evolved.
One aspect of the present invention relates to maintaining cache coherency in a computer system that has a bus system that does not support bus snooping, such as AHB (Advanced High-Performance Bus). The invention also relates to including bus snooping in a computer system having a bus system that does not have a bus signal that enables bus snooping. The invention also relates to a stand-alone bus snooping device, separate from the bus system and the devices that include caching capabilities (caching devices).
Generally, a new and improved bus snooping device monitors, or xe2x80x9csnoops,xe2x80x9d information transfer activity on the bus system on behalf of one or more caching devices to determine when cached information is about to be changed in a xe2x80x9cslavexe2x80x9d device, such as a main computer memory or other receiving device, so that the cached copy of the information must be invalidated. The protocol under which the bus system operates preferably includes a xe2x80x9creadyxe2x80x9d signal which the slave device asserts to signal a xe2x80x9cmasterxe2x80x9d device, such as a CPU (central processing unit), DMA (direct memory access) or other sending device, that it is ready to receive the information transfer. The bus snooping device intercepts, disables or delays the ready signal until it can determine whether the cached information must be invalidated in the caching device. In this manner, the bus snooping device enables bus snooping capabilities for a bus system that does not include built-in support for bus snooping.
The bus system is preferably a xe2x80x9csystem bus,xe2x80x9d such as the AHB, instead of a peripheral bus, since the CPU(s), any other caching devices and other master and/or slave devices typically connect to the system bus of a computer. System. buses, however, are typically proprietary, instead of industry standards, or widely accepted de facto standards, such as PCI (Peripheral Component Interconnect) and ISA (Industry Standard Architecture) are for peripheral buses. The AHB, for example, is a proprietary system bus that has been incorporated into computer systems by several computer makers. The AHB supports multiple CPU""s, but does not allow the CPU""s to share memory space since it does not support bus snooping. Therefore, without changing any aspect of the AHB, the present invention enables bus snooping and the incorporation of multiple memory-sharing CPU""s in a computer system having an AHB.